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Makefile example

Some time ago I created my first Makefile. Now I have an Embedded Linux lecture. And the first task is to create a Makefile for the program. I hope this will be useful. So, I have two source files:
/* first.c */ #include "all_func.h" int foo() { printf("int foo()\r\n"); } /* second.c */ #include "all_func.h" void foo2() { printf("void foo2()\r\n"); }
And I also have a header file:
/* all_func.h */ #ifndef ALL_FUNC_H #define ALL_FUNC_H #include int foo(); void foo2(); #endif
I also need one file for testing my functions:
/* test.c */ #include "all_func.h" int main() { foo(); foo2(); }
So, I need to build all this mess. Solution: gcc first.c second.c test.c -o test. The problem: if I'll have more files the gcc line will be too huge. Solution: create a makefile. The problem: it takes some time to create one if you don't use IDE for creating your project. Well, let's make a Makefile. It looks like that:
# File: Makefile # Makefile for my Embedded Linux assignment CC = gcc CFLAGS = -Wall CMDTEST = test_all LIBOBJS = first.o second.o CMDOBJS = test.o $(LIBOBJS) # Make a test application $(CMDTEST): $(CMDOBJS) $(CC) $(CFLAGS) $(CMDOBJS) -o $@ # Make object file from the first file first.o: first.c all_func.h $(CC) $(CFLAGS) -c first.c -o $@ # Make object file from the second file second.o: second.c all_func.h $(CC) $(CFLAGS) -c second.c -o $@ clean: -rm -f *.o -rm -f $(LIBRARY) -rm -f $(CMDTEST)
It works! Try make or make clean :)


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